/**
 * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
 *
 *  SPDX-License-Identifier: Apache-2.0 OR MIT
 */
#pragma once

#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif

/** LP_PERICLKRST_CPU_CTRL_REG register
 *  need_des
 */
#define LP_PERICLKRST_CPU_CTRL_REG (DR_REG_LP_PERICLKRST_BASE + 0x4)
/** LP_PERICLKRST_LP_CORE_CLK_FORCE_ON : R/W; bitpos: [30]; default: 0;
 *  need_des
 */
#define LP_PERICLKRST_LP_CORE_CLK_FORCE_ON    (BIT(30))
#define LP_PERICLKRST_LP_CORE_CLK_FORCE_ON_M  (LP_PERICLKRST_LP_CORE_CLK_FORCE_ON_V << LP_PERICLKRST_LP_CORE_CLK_FORCE_ON_S)
#define LP_PERICLKRST_LP_CORE_CLK_FORCE_ON_V  0x00000001U
#define LP_PERICLKRST_LP_CORE_CLK_FORCE_ON_S  30
/** LP_PERICLKRST_LP_CORE_RST_EN : WT; bitpos: [31]; default: 0;
 *  need_des
 */
#define LP_PERICLKRST_LP_CORE_RST_EN    (BIT(31))
#define LP_PERICLKRST_LP_CORE_RST_EN_M  (LP_PERICLKRST_LP_CORE_RST_EN_V << LP_PERICLKRST_LP_CORE_RST_EN_S)
#define LP_PERICLKRST_LP_CORE_RST_EN_V  0x00000001U
#define LP_PERICLKRST_LP_CORE_RST_EN_S  31

/** LP_PERICLKRST_ROM_CTRL_REG register
 *  need_des
 */
#define LP_PERICLKRST_ROM_CTRL_REG (DR_REG_LP_PERICLKRST_BASE + 0x8)
/** LP_PERICLKRST_LP_ROM_FORCE_ON : R/W; bitpos: [30]; default: 0;
 *  need_des
 */
#define LP_PERICLKRST_LP_ROM_FORCE_ON    (BIT(30))
#define LP_PERICLKRST_LP_ROM_FORCE_ON_M  (LP_PERICLKRST_LP_ROM_FORCE_ON_V << LP_PERICLKRST_LP_ROM_FORCE_ON_S)
#define LP_PERICLKRST_LP_ROM_FORCE_ON_V  0x00000001U
#define LP_PERICLKRST_LP_ROM_FORCE_ON_S  30
/** LP_PERICLKRST_LP_ROM_RST_EN : R/W; bitpos: [31]; default: 0;
 *  need_des
 */
#define LP_PERICLKRST_LP_ROM_RST_EN    (BIT(31))
#define LP_PERICLKRST_LP_ROM_RST_EN_M  (LP_PERICLKRST_LP_ROM_RST_EN_V << LP_PERICLKRST_LP_ROM_RST_EN_S)
#define LP_PERICLKRST_LP_ROM_RST_EN_V  0x00000001U
#define LP_PERICLKRST_LP_ROM_RST_EN_S  31

/** LP_PERICLKRST_RAM_CTRL_REG register
 *  need_des
 */
#define LP_PERICLKRST_RAM_CTRL_REG (DR_REG_LP_PERICLKRST_BASE + 0xc)
/** LP_PERICLKRST_LP_RAM_CLK_EN : R/W; bitpos: [30]; default: 1;
 *  need_des
 */
#define LP_PERICLKRST_LP_RAM_CLK_EN    (BIT(30))
#define LP_PERICLKRST_LP_RAM_CLK_EN_M  (LP_PERICLKRST_LP_RAM_CLK_EN_V << LP_PERICLKRST_LP_RAM_CLK_EN_S)
#define LP_PERICLKRST_LP_RAM_CLK_EN_V  0x00000001U
#define LP_PERICLKRST_LP_RAM_CLK_EN_S  30
/** LP_PERICLKRST_LP_RAM_RST_EN : R/W; bitpos: [31]; default: 0;
 *  need_des
 */
#define LP_PERICLKRST_LP_RAM_RST_EN    (BIT(31))
#define LP_PERICLKRST_LP_RAM_RST_EN_M  (LP_PERICLKRST_LP_RAM_RST_EN_V << LP_PERICLKRST_LP_RAM_RST_EN_S)
#define LP_PERICLKRST_LP_RAM_RST_EN_V  0x00000001U
#define LP_PERICLKRST_LP_RAM_RST_EN_S  31

/** LP_PERICLKRST_UART_CTRL_REG register
 *  need_des
 */
#define LP_PERICLKRST_UART_CTRL_REG (DR_REG_LP_PERICLKRST_BASE + 0x10)
/** LP_PERICLKRST_LP_UART_CLK_DIV_NUM : R/W; bitpos: [27:20]; default: 0;
 *  need_des
 */
#define LP_PERICLKRST_LP_UART_CLK_DIV_NUM    0x000000FFU
#define LP_PERICLKRST_LP_UART_CLK_DIV_NUM_M  (LP_PERICLKRST_LP_UART_CLK_DIV_NUM_V << LP_PERICLKRST_LP_UART_CLK_DIV_NUM_S)
#define LP_PERICLKRST_LP_UART_CLK_DIV_NUM_V  0x000000FFU
#define LP_PERICLKRST_LP_UART_CLK_DIV_NUM_S  20
/** LP_PERICLKRST_LP_UART_CLK_SEL : R/W; bitpos: [29:28]; default: 0;
 *  need_des
 */
#define LP_PERICLKRST_LP_UART_CLK_SEL    0x00000003U
#define LP_PERICLKRST_LP_UART_CLK_SEL_M  (LP_PERICLKRST_LP_UART_CLK_SEL_V << LP_PERICLKRST_LP_UART_CLK_SEL_S)
#define LP_PERICLKRST_LP_UART_CLK_SEL_V  0x00000003U
#define LP_PERICLKRST_LP_UART_CLK_SEL_S  28
/** LP_PERICLKRST_LP_UART_CLK_EN : R/W; bitpos: [30]; default: 0;
 *  need_des
 */
#define LP_PERICLKRST_LP_UART_CLK_EN    (BIT(30))
#define LP_PERICLKRST_LP_UART_CLK_EN_M  (LP_PERICLKRST_LP_UART_CLK_EN_V << LP_PERICLKRST_LP_UART_CLK_EN_S)
#define LP_PERICLKRST_LP_UART_CLK_EN_V  0x00000001U
#define LP_PERICLKRST_LP_UART_CLK_EN_S  30
/** LP_PERICLKRST_LP_UART_RST_EN : R/W; bitpos: [31]; default: 0;
 *  need_des
 */
#define LP_PERICLKRST_LP_UART_RST_EN    (BIT(31))
#define LP_PERICLKRST_LP_UART_RST_EN_M  (LP_PERICLKRST_LP_UART_RST_EN_V << LP_PERICLKRST_LP_UART_RST_EN_S)
#define LP_PERICLKRST_LP_UART_RST_EN_V  0x00000001U
#define LP_PERICLKRST_LP_UART_RST_EN_S  31

/** LP_PERICLKRST_I2C_CTRL_REG register
 *  need_des
 */
#define LP_PERICLKRST_I2C_CTRL_REG (DR_REG_LP_PERICLKRST_BASE + 0x14)
/** LP_PERICLKRST_LP_I2C_CLK_DIV_NUM : R/W; bitpos: [27:20]; default: 0;
 *  need_des
 */
#define LP_PERICLKRST_LP_I2C_CLK_DIV_NUM    0x000000FFU
#define LP_PERICLKRST_LP_I2C_CLK_DIV_NUM_M  (LP_PERICLKRST_LP_I2C_CLK_DIV_NUM_V << LP_PERICLKRST_LP_I2C_CLK_DIV_NUM_S)
#define LP_PERICLKRST_LP_I2C_CLK_DIV_NUM_V  0x000000FFU
#define LP_PERICLKRST_LP_I2C_CLK_DIV_NUM_S  20
/** LP_PERICLKRST_LP_I2C_CLK_SEL : R/W; bitpos: [29:28]; default: 0;
 *  need_des
 */
#define LP_PERICLKRST_LP_I2C_CLK_SEL    0x00000003U
#define LP_PERICLKRST_LP_I2C_CLK_SEL_M  (LP_PERICLKRST_LP_I2C_CLK_SEL_V << LP_PERICLKRST_LP_I2C_CLK_SEL_S)
#define LP_PERICLKRST_LP_I2C_CLK_SEL_V  0x00000003U
#define LP_PERICLKRST_LP_I2C_CLK_SEL_S  28
/** LP_PERICLKRST_LP_I2C_CLK_EN : R/W; bitpos: [30]; default: 0;
 *  need_des
 */
#define LP_PERICLKRST_LP_I2C_CLK_EN    (BIT(30))
#define LP_PERICLKRST_LP_I2C_CLK_EN_M  (LP_PERICLKRST_LP_I2C_CLK_EN_V << LP_PERICLKRST_LP_I2C_CLK_EN_S)
#define LP_PERICLKRST_LP_I2C_CLK_EN_V  0x00000001U
#define LP_PERICLKRST_LP_I2C_CLK_EN_S  30
/** LP_PERICLKRST_LP_I2C_RST_EN : R/W; bitpos: [31]; default: 0;
 *  need_des
 */
#define LP_PERICLKRST_LP_I2C_RST_EN    (BIT(31))
#define LP_PERICLKRST_LP_I2C_RST_EN_M  (LP_PERICLKRST_LP_I2C_RST_EN_V << LP_PERICLKRST_LP_I2C_RST_EN_S)
#define LP_PERICLKRST_LP_I2C_RST_EN_V  0x00000001U
#define LP_PERICLKRST_LP_I2C_RST_EN_S  31

/** LP_PERICLKRST_I2CMST_CTRL_REG register
 *  need_des
 */
#define LP_PERICLKRST_I2CMST_CTRL_REG (DR_REG_LP_PERICLKRST_BASE + 0x18)
/** LP_PERICLKRST_LP_I2CMST_CLK_EN : R/W; bitpos: [30]; default: 1;
 *  need_des
 */
#define LP_PERICLKRST_LP_I2CMST_CLK_EN    (BIT(30))
#define LP_PERICLKRST_LP_I2CMST_CLK_EN_M  (LP_PERICLKRST_LP_I2CMST_CLK_EN_V << LP_PERICLKRST_LP_I2CMST_CLK_EN_S)
#define LP_PERICLKRST_LP_I2CMST_CLK_EN_V  0x00000001U
#define LP_PERICLKRST_LP_I2CMST_CLK_EN_S  30
/** LP_PERICLKRST_LP_I2CMST_RST_EN : R/W; bitpos: [31]; default: 0;
 *  need_des
 */
#define LP_PERICLKRST_LP_I2CMST_RST_EN    (BIT(31))
#define LP_PERICLKRST_LP_I2CMST_RST_EN_M  (LP_PERICLKRST_LP_I2CMST_RST_EN_V << LP_PERICLKRST_LP_I2CMST_RST_EN_S)
#define LP_PERICLKRST_LP_I2CMST_RST_EN_V  0x00000001U
#define LP_PERICLKRST_LP_I2CMST_RST_EN_S  31

/** LP_PERICLKRST_SPI_CTRL_REG register
 *  need_des
 */
#define LP_PERICLKRST_SPI_CTRL_REG (DR_REG_LP_PERICLKRST_BASE + 0x1c)
/** LP_PERICLKRST_LP_SPI_CLK_EN : R/W; bitpos: [30]; default: 0;
 *  need_des
 */
#define LP_PERICLKRST_LP_SPI_CLK_EN    (BIT(30))
#define LP_PERICLKRST_LP_SPI_CLK_EN_M  (LP_PERICLKRST_LP_SPI_CLK_EN_V << LP_PERICLKRST_LP_SPI_CLK_EN_S)
#define LP_PERICLKRST_LP_SPI_CLK_EN_V  0x00000001U
#define LP_PERICLKRST_LP_SPI_CLK_EN_S  30
/** LP_PERICLKRST_LP_SPI_RST_EN : R/W; bitpos: [31]; default: 0;
 *  need_des
 */
#define LP_PERICLKRST_LP_SPI_RST_EN    (BIT(31))
#define LP_PERICLKRST_LP_SPI_RST_EN_M  (LP_PERICLKRST_LP_SPI_RST_EN_V << LP_PERICLKRST_LP_SPI_RST_EN_S)
#define LP_PERICLKRST_LP_SPI_RST_EN_V  0x00000001U
#define LP_PERICLKRST_LP_SPI_RST_EN_S  31

/** LP_PERICLKRST_ADC_CTRL_REG register
 *  need_des
 */
#define LP_PERICLKRST_ADC_CTRL_REG (DR_REG_LP_PERICLKRST_BASE + 0x20)
/** LP_PERICLKRST_LP_ADC_DIV_NUM : R/W; bitpos: [7:0]; default: 4;
 *  need_des
 */
#define LP_PERICLKRST_LP_ADC_DIV_NUM    0x000000FFU
#define LP_PERICLKRST_LP_ADC_DIV_NUM_M  (LP_PERICLKRST_LP_ADC_DIV_NUM_V << LP_PERICLKRST_LP_ADC_DIV_NUM_S)
#define LP_PERICLKRST_LP_ADC_DIV_NUM_V  0x000000FFU
#define LP_PERICLKRST_LP_ADC_DIV_NUM_S  0
/** LP_PERICLKRST_LP_ADC_CLK_SEL : R/W; bitpos: [29:28]; default: 0;
 *  need_des
 */
#define LP_PERICLKRST_LP_ADC_CLK_SEL    0x00000003U
#define LP_PERICLKRST_LP_ADC_CLK_SEL_M  (LP_PERICLKRST_LP_ADC_CLK_SEL_V << LP_PERICLKRST_LP_ADC_CLK_SEL_S)
#define LP_PERICLKRST_LP_ADC_CLK_SEL_V  0x00000003U
#define LP_PERICLKRST_LP_ADC_CLK_SEL_S  28
/** LP_PERICLKRST_LP_ADC_CLK_EN : R/W; bitpos: [30]; default: 1;
 *  need_des
 */
#define LP_PERICLKRST_LP_ADC_CLK_EN    (BIT(30))
#define LP_PERICLKRST_LP_ADC_CLK_EN_M  (LP_PERICLKRST_LP_ADC_CLK_EN_V << LP_PERICLKRST_LP_ADC_CLK_EN_S)
#define LP_PERICLKRST_LP_ADC_CLK_EN_V  0x00000001U
#define LP_PERICLKRST_LP_ADC_CLK_EN_S  30
/** LP_PERICLKRST_LP_ADC_RST_EN : R/W; bitpos: [31]; default: 0;
 *  need_des
 */
#define LP_PERICLKRST_LP_ADC_RST_EN    (BIT(31))
#define LP_PERICLKRST_LP_ADC_RST_EN_M  (LP_PERICLKRST_LP_ADC_RST_EN_V << LP_PERICLKRST_LP_ADC_RST_EN_S)
#define LP_PERICLKRST_LP_ADC_RST_EN_V  0x00000001U
#define LP_PERICLKRST_LP_ADC_RST_EN_S  31

/** LP_PERICLKRST_EFUSE_CTRL_REG register
 *  need_des
 */
#define LP_PERICLKRST_EFUSE_CTRL_REG (DR_REG_LP_PERICLKRST_BASE + 0x24)
/** LP_PERICLKRST_LP_EFUSE_CLK_EN : R/W; bitpos: [30]; default: 1;
 *  need_des
 */
#define LP_PERICLKRST_LP_EFUSE_CLK_EN    (BIT(30))
#define LP_PERICLKRST_LP_EFUSE_CLK_EN_M  (LP_PERICLKRST_LP_EFUSE_CLK_EN_V << LP_PERICLKRST_LP_EFUSE_CLK_EN_S)
#define LP_PERICLKRST_LP_EFUSE_CLK_EN_V  0x00000001U
#define LP_PERICLKRST_LP_EFUSE_CLK_EN_S  30
/** LP_PERICLKRST_LP_EFUSE_RST_EN : R/W; bitpos: [31]; default: 0;
 *  need_des
 */
#define LP_PERICLKRST_LP_EFUSE_RST_EN    (BIT(31))
#define LP_PERICLKRST_LP_EFUSE_RST_EN_M  (LP_PERICLKRST_LP_EFUSE_RST_EN_V << LP_PERICLKRST_LP_EFUSE_RST_EN_S)
#define LP_PERICLKRST_LP_EFUSE_RST_EN_V  0x00000001U
#define LP_PERICLKRST_LP_EFUSE_RST_EN_S  31

/** LP_PERICLKRST_INTR_CTRL_REG register
 *  need_des
 */
#define LP_PERICLKRST_INTR_CTRL_REG (DR_REG_LP_PERICLKRST_BASE + 0x28)
/** LP_PERICLKRST_LP_INTR_CLK_EN : R/W; bitpos: [30]; default: 0;
 *  need_des
 */
#define LP_PERICLKRST_LP_INTR_CLK_EN    (BIT(30))
#define LP_PERICLKRST_LP_INTR_CLK_EN_M  (LP_PERICLKRST_LP_INTR_CLK_EN_V << LP_PERICLKRST_LP_INTR_CLK_EN_S)
#define LP_PERICLKRST_LP_INTR_CLK_EN_V  0x00000001U
#define LP_PERICLKRST_LP_INTR_CLK_EN_S  30
/** LP_PERICLKRST_LP_INTR_RST_EN : R/W; bitpos: [31]; default: 0;
 *  need_des
 */
#define LP_PERICLKRST_LP_INTR_RST_EN    (BIT(31))
#define LP_PERICLKRST_LP_INTR_RST_EN_M  (LP_PERICLKRST_LP_INTR_RST_EN_V << LP_PERICLKRST_LP_INTR_RST_EN_S)
#define LP_PERICLKRST_LP_INTR_RST_EN_V  0x00000001U
#define LP_PERICLKRST_LP_INTR_RST_EN_S  31

/** LP_PERICLKRST_TOUCH_CTRL_REG register
 *  need_des
 */
#define LP_PERICLKRST_TOUCH_CTRL_REG (DR_REG_LP_PERICLKRST_BASE + 0x2c)
/** LP_PERICLKRST_LP_TOUCH_CLK_EN : R/W; bitpos: [30]; default: 1;
 *  need_des
 */
#define LP_PERICLKRST_LP_TOUCH_CLK_EN    (BIT(30))
#define LP_PERICLKRST_LP_TOUCH_CLK_EN_M  (LP_PERICLKRST_LP_TOUCH_CLK_EN_V << LP_PERICLKRST_LP_TOUCH_CLK_EN_S)
#define LP_PERICLKRST_LP_TOUCH_CLK_EN_V  0x00000001U
#define LP_PERICLKRST_LP_TOUCH_CLK_EN_S  30
/** LP_PERICLKRST_LP_TOUCH_RST_EN : R/W; bitpos: [31]; default: 0;
 *  need_des
 */
#define LP_PERICLKRST_LP_TOUCH_RST_EN    (BIT(31))
#define LP_PERICLKRST_LP_TOUCH_RST_EN_M  (LP_PERICLKRST_LP_TOUCH_RST_EN_V << LP_PERICLKRST_LP_TOUCH_RST_EN_S)
#define LP_PERICLKRST_LP_TOUCH_RST_EN_V  0x00000001U
#define LP_PERICLKRST_LP_TOUCH_RST_EN_S  31

/** LP_PERICLKRST_TSENS_CTRL_REG register
 *  need_des
 */
#define LP_PERICLKRST_TSENS_CTRL_REG (DR_REG_LP_PERICLKRST_BASE + 0x30)
/** LP_PERICLKRST_LP_TSENS_CLK_EN : R/W; bitpos: [30]; default: 0;
 *  need_des
 */
#define LP_PERICLKRST_LP_TSENS_CLK_EN    (BIT(30))
#define LP_PERICLKRST_LP_TSENS_CLK_EN_M  (LP_PERICLKRST_LP_TSENS_CLK_EN_V << LP_PERICLKRST_LP_TSENS_CLK_EN_S)
#define LP_PERICLKRST_LP_TSENS_CLK_EN_V  0x00000001U
#define LP_PERICLKRST_LP_TSENS_CLK_EN_S  30
/** LP_PERICLKRST_LP_TSENS_RST_EN : R/W; bitpos: [31]; default: 0;
 *  need_des
 */
#define LP_PERICLKRST_LP_TSENS_RST_EN    (BIT(31))
#define LP_PERICLKRST_LP_TSENS_RST_EN_M  (LP_PERICLKRST_LP_TSENS_RST_EN_V << LP_PERICLKRST_LP_TSENS_RST_EN_S)
#define LP_PERICLKRST_LP_TSENS_RST_EN_V  0x00000001U
#define LP_PERICLKRST_LP_TSENS_RST_EN_S  31

/** LP_PERICLKRST_IOMUX_CTRL_REG register
 *  need_des
 */
#define LP_PERICLKRST_IOMUX_CTRL_REG (DR_REG_LP_PERICLKRST_BASE + 0x34)
/** LP_PERICLKRST_LP_IOMUX_CLK_EN : R/W; bitpos: [30]; default: 1;
 *  need_des
 */
#define LP_PERICLKRST_LP_IOMUX_CLK_EN    (BIT(30))
#define LP_PERICLKRST_LP_IOMUX_CLK_EN_M  (LP_PERICLKRST_LP_IOMUX_CLK_EN_V << LP_PERICLKRST_LP_IOMUX_CLK_EN_S)
#define LP_PERICLKRST_LP_IOMUX_CLK_EN_V  0x00000001U
#define LP_PERICLKRST_LP_IOMUX_CLK_EN_S  30
/** LP_PERICLKRST_LP_IOMUX_RST_EN : R/W; bitpos: [31]; default: 0;
 *  need_des
 */
#define LP_PERICLKRST_LP_IOMUX_RST_EN    (BIT(31))
#define LP_PERICLKRST_LP_IOMUX_RST_EN_M  (LP_PERICLKRST_LP_IOMUX_RST_EN_V << LP_PERICLKRST_LP_IOMUX_RST_EN_S)
#define LP_PERICLKRST_LP_IOMUX_RST_EN_V  0x00000001U
#define LP_PERICLKRST_LP_IOMUX_RST_EN_S  31

/** LP_PERICLKRST_MAILBOX_REG register
 *  need_des
 */
#define LP_PERICLKRST_MAILBOX_REG (DR_REG_LP_PERICLKRST_BASE + 0x38)
/** LP_PERICLKRST_LP_MAILBOX_CLK_EN : R/W; bitpos: [30]; default: 0;
 *  need_des
 */
#define LP_PERICLKRST_LP_MAILBOX_CLK_EN    (BIT(30))
#define LP_PERICLKRST_LP_MAILBOX_CLK_EN_M  (LP_PERICLKRST_LP_MAILBOX_CLK_EN_V << LP_PERICLKRST_LP_MAILBOX_CLK_EN_S)
#define LP_PERICLKRST_LP_MAILBOX_CLK_EN_V  0x00000001U
#define LP_PERICLKRST_LP_MAILBOX_CLK_EN_S  30
/** LP_PERICLKRST_LP_MAILBOX_RST_EN : R/W; bitpos: [31]; default: 0;
 *  need_des
 */
#define LP_PERICLKRST_LP_MAILBOX_RST_EN    (BIT(31))
#define LP_PERICLKRST_LP_MAILBOX_RST_EN_M  (LP_PERICLKRST_LP_MAILBOX_RST_EN_V << LP_PERICLKRST_LP_MAILBOX_RST_EN_S)
#define LP_PERICLKRST_LP_MAILBOX_RST_EN_V  0x00000001U
#define LP_PERICLKRST_LP_MAILBOX_RST_EN_S  31

/** LP_PERICLKRST_RNG_CTRL_REG register
 *  need_des
 */
#define LP_PERICLKRST_RNG_CTRL_REG (DR_REG_LP_PERICLKRST_BASE + 0x3c)
/** LP_PERICLKRST_LP_RNG_CLK_EN : R/W; bitpos: [30]; default: 1;
 *  need_des
 */
#define LP_PERICLKRST_LP_RNG_CLK_EN    (BIT(30))
#define LP_PERICLKRST_LP_RNG_CLK_EN_M  (LP_PERICLKRST_LP_RNG_CLK_EN_V << LP_PERICLKRST_LP_RNG_CLK_EN_S)
#define LP_PERICLKRST_LP_RNG_CLK_EN_V  0x00000001U
#define LP_PERICLKRST_LP_RNG_CLK_EN_S  30
/** LP_PERICLKRST_LP_RNG_RST_EN : R/W; bitpos: [31]; default: 0;
 *  need_des
 */
#define LP_PERICLKRST_LP_RNG_RST_EN    (BIT(31))
#define LP_PERICLKRST_LP_RNG_RST_EN_M  (LP_PERICLKRST_LP_RNG_RST_EN_V << LP_PERICLKRST_LP_RNG_RST_EN_S)
#define LP_PERICLKRST_LP_RNG_RST_EN_V  0x00000001U
#define LP_PERICLKRST_LP_RNG_RST_EN_S  31

/** LP_PERICLKRST_UART_MISC_CTRL_REG register
 *  need_des
 */
#define LP_PERICLKRST_UART_MISC_CTRL_REG (DR_REG_LP_PERICLKRST_BASE + 0x40)
/** LP_PERICLKRST_LP_UART_WAKEUP_FLAG_CLR : WT; bitpos: [0]; default: 0;
 *  need_des
 */
#define LP_PERICLKRST_LP_UART_WAKEUP_FLAG_CLR    (BIT(0))
#define LP_PERICLKRST_LP_UART_WAKEUP_FLAG_CLR_M  (LP_PERICLKRST_LP_UART_WAKEUP_FLAG_CLR_V << LP_PERICLKRST_LP_UART_WAKEUP_FLAG_CLR_S)
#define LP_PERICLKRST_LP_UART_WAKEUP_FLAG_CLR_V  0x00000001U
#define LP_PERICLKRST_LP_UART_WAKEUP_FLAG_CLR_S  0
/** LP_PERICLKRST_LP_UART_WAKEUP_FLAG : R/WTC/SS; bitpos: [1]; default: 0;
 *  need_des
 */
#define LP_PERICLKRST_LP_UART_WAKEUP_FLAG    (BIT(1))
#define LP_PERICLKRST_LP_UART_WAKEUP_FLAG_M  (LP_PERICLKRST_LP_UART_WAKEUP_FLAG_V << LP_PERICLKRST_LP_UART_WAKEUP_FLAG_S)
#define LP_PERICLKRST_LP_UART_WAKEUP_FLAG_V  0x00000001U
#define LP_PERICLKRST_LP_UART_WAKEUP_FLAG_S  1
/** LP_PERICLKRST_LP_UART_WAKEUP_EN : R/W; bitpos: [29]; default: 0;
 *  need_des
 */
#define LP_PERICLKRST_LP_UART_WAKEUP_EN    (BIT(29))
#define LP_PERICLKRST_LP_UART_WAKEUP_EN_M  (LP_PERICLKRST_LP_UART_WAKEUP_EN_V << LP_PERICLKRST_LP_UART_WAKEUP_EN_S)
#define LP_PERICLKRST_LP_UART_WAKEUP_EN_V  0x00000001U
#define LP_PERICLKRST_LP_UART_WAKEUP_EN_S  29
/** LP_PERICLKRST_LP_UART_MEM_FORCE_PD : R/W; bitpos: [30]; default: 1;
 *  need_des
 */
#define LP_PERICLKRST_LP_UART_MEM_FORCE_PD    (BIT(30))
#define LP_PERICLKRST_LP_UART_MEM_FORCE_PD_M  (LP_PERICLKRST_LP_UART_MEM_FORCE_PD_V << LP_PERICLKRST_LP_UART_MEM_FORCE_PD_S)
#define LP_PERICLKRST_LP_UART_MEM_FORCE_PD_V  0x00000001U
#define LP_PERICLKRST_LP_UART_MEM_FORCE_PD_S  30
/** LP_PERICLKRST_LP_UART_MEM_FORCE_PU : R/W; bitpos: [31]; default: 0;
 *  need_des
 */
#define LP_PERICLKRST_LP_UART_MEM_FORCE_PU    (BIT(31))
#define LP_PERICLKRST_LP_UART_MEM_FORCE_PU_M  (LP_PERICLKRST_LP_UART_MEM_FORCE_PU_V << LP_PERICLKRST_LP_UART_MEM_FORCE_PU_S)
#define LP_PERICLKRST_LP_UART_MEM_FORCE_PU_V  0x00000001U
#define LP_PERICLKRST_LP_UART_MEM_FORCE_PU_S  31

/** LP_PERICLKRST_CPU_REG register
 *  need_des
 */
#define LP_PERICLKRST_CPU_REG (DR_REG_LP_PERICLKRST_BASE + 0x44)
/** LP_PERICLKRST_LPCORE_DBGM_UNAVAILABLE : R/W; bitpos: [31]; default: 1;
 *  need_des
 */
#define LP_PERICLKRST_LPCORE_DBGM_UNAVAILABLE    (BIT(31))
#define LP_PERICLKRST_LPCORE_DBGM_UNAVAILABLE_M  (LP_PERICLKRST_LPCORE_DBGM_UNAVAILABLE_V << LP_PERICLKRST_LPCORE_DBGM_UNAVAILABLE_S)
#define LP_PERICLKRST_LPCORE_DBGM_UNAVAILABLE_V  0x00000001U
#define LP_PERICLKRST_LPCORE_DBGM_UNAVAILABLE_S  31

/** LP_PERICLKRST_AHB_DMA_CTRL_REG register
 *  need_des
 */
#define LP_PERICLKRST_AHB_DMA_CTRL_REG (DR_REG_LP_PERICLKRST_BASE + 0x48)
/** LP_PERICLKRST_LP_AHB_DMA_CLK_EN : R/W; bitpos: [30]; default: 0;
 *  need_des
 */
#define LP_PERICLKRST_LP_AHB_DMA_CLK_EN    (BIT(30))
#define LP_PERICLKRST_LP_AHB_DMA_CLK_EN_M  (LP_PERICLKRST_LP_AHB_DMA_CLK_EN_V << LP_PERICLKRST_LP_AHB_DMA_CLK_EN_S)
#define LP_PERICLKRST_LP_AHB_DMA_CLK_EN_V  0x00000001U
#define LP_PERICLKRST_LP_AHB_DMA_CLK_EN_S  30
/** LP_PERICLKRST_LP_AHB_DMA_RST_EN : R/W; bitpos: [31]; default: 0;
 *  need_des
 */
#define LP_PERICLKRST_LP_AHB_DMA_RST_EN    (BIT(31))
#define LP_PERICLKRST_LP_AHB_DMA_RST_EN_M  (LP_PERICLKRST_LP_AHB_DMA_RST_EN_V << LP_PERICLKRST_LP_AHB_DMA_RST_EN_S)
#define LP_PERICLKRST_LP_AHB_DMA_RST_EN_V  0x00000001U
#define LP_PERICLKRST_LP_AHB_DMA_RST_EN_S  31

/** LP_PERICLKRST_DAC_CTRL_REG register
 *  need_des
 */
#define LP_PERICLKRST_DAC_CTRL_REG (DR_REG_LP_PERICLKRST_BASE + 0x4c)
/** LP_PERICLKRST_LP_DAC_DIV_NUM : R/W; bitpos: [7:0]; default: 4;
 *  need_des
 */
#define LP_PERICLKRST_LP_DAC_DIV_NUM    0x000000FFU
#define LP_PERICLKRST_LP_DAC_DIV_NUM_M  (LP_PERICLKRST_LP_DAC_DIV_NUM_V << LP_PERICLKRST_LP_DAC_DIV_NUM_S)
#define LP_PERICLKRST_LP_DAC_DIV_NUM_V  0x000000FFU
#define LP_PERICLKRST_LP_DAC_DIV_NUM_S  0
/** LP_PERICLKRST_LP_DAC_CLK_SEL : R/W; bitpos: [29:28]; default: 0;
 *  need_des
 */
#define LP_PERICLKRST_LP_DAC_CLK_SEL    0x00000003U
#define LP_PERICLKRST_LP_DAC_CLK_SEL_M  (LP_PERICLKRST_LP_DAC_CLK_SEL_V << LP_PERICLKRST_LP_DAC_CLK_SEL_S)
#define LP_PERICLKRST_LP_DAC_CLK_SEL_V  0x00000003U
#define LP_PERICLKRST_LP_DAC_CLK_SEL_S  28
/** LP_PERICLKRST_LP_DAC_CLK_EN : R/W; bitpos: [30]; default: 0;
 *  need_des
 */
#define LP_PERICLKRST_LP_DAC_CLK_EN    (BIT(30))
#define LP_PERICLKRST_LP_DAC_CLK_EN_M  (LP_PERICLKRST_LP_DAC_CLK_EN_V << LP_PERICLKRST_LP_DAC_CLK_EN_S)
#define LP_PERICLKRST_LP_DAC_CLK_EN_V  0x00000001U
#define LP_PERICLKRST_LP_DAC_CLK_EN_S  30
/** LP_PERICLKRST_LP_DAC_RST_EN : R/W; bitpos: [31]; default: 0;
 *  need_des
 */
#define LP_PERICLKRST_LP_DAC_RST_EN    (BIT(31))
#define LP_PERICLKRST_LP_DAC_RST_EN_M  (LP_PERICLKRST_LP_DAC_RST_EN_V << LP_PERICLKRST_LP_DAC_RST_EN_S)
#define LP_PERICLKRST_LP_DAC_RST_EN_V  0x00000001U
#define LP_PERICLKRST_LP_DAC_RST_EN_S  31

/** LP_PERICLKRST_DM_CTRL_REG register
 *  need_des
 */
#define LP_PERICLKRST_DM_CTRL_REG (DR_REG_LP_PERICLKRST_BASE + 0x50)
/** LP_PERICLKRST_LP_DM_CLK_EN : R/W; bitpos: [31]; default: 1;
 *  need_des
 */
#define LP_PERICLKRST_LP_DM_CLK_EN    (BIT(31))
#define LP_PERICLKRST_LP_DM_CLK_EN_M  (LP_PERICLKRST_LP_DM_CLK_EN_V << LP_PERICLKRST_LP_DM_CLK_EN_S)
#define LP_PERICLKRST_LP_DM_CLK_EN_V  0x00000001U
#define LP_PERICLKRST_LP_DM_CLK_EN_S  31

/** LP_PERICLKRST_DATE_REG register
 *  need_des
 */
#define LP_PERICLKRST_DATE_REG (DR_REG_LP_PERICLKRST_BASE + 0x3fc)
/** LP_PERICLKRST_DATE : R/W; bitpos: [30:0]; default: 38834448;
 *  need_des
 */
#define LP_PERICLKRST_DATE    0x7FFFFFFFU
#define LP_PERICLKRST_DATE_M  (LP_PERICLKRST_DATE_V << LP_PERICLKRST_DATE_S)
#define LP_PERICLKRST_DATE_V  0x7FFFFFFFU
#define LP_PERICLKRST_DATE_S  0
/** LP_PERICLKRST_CLK_EN : R/W; bitpos: [31]; default: 0;
 *  need_des
 */
#define LP_PERICLKRST_CLK_EN    (BIT(31))
#define LP_PERICLKRST_CLK_EN_M  (LP_PERICLKRST_CLK_EN_V << LP_PERICLKRST_CLK_EN_S)
#define LP_PERICLKRST_CLK_EN_V  0x00000001U
#define LP_PERICLKRST_CLK_EN_S  31

#ifdef __cplusplus
}
#endif
